The present invention relates to automobile engines, and, more particularly, to electronic control units for automobile engines.
In automotive engines, electronic control units (ECUs) are used for driving actuator devices associated with the engines. ECUs include a central processing unit, such as a microprocessor, that controls the operation of the actuator devices via low power control signals. Each actuator device has an associated driver to raise the power of the control signals to a level sufficient to allow actuation. Multiple drivers can be formed in a single integrated semiconductor circuit.
For the engine to operate correctly, the central processing unit of the ECU requires a complete analysis of the operating state of the drivers in their different operating phases to detect temporary anomalies (for example, a short circuit to ground, a short circuit to the battery, and an open circuit to load) and take the corrective action. Diagnosis circuits are provided for this purpose that are associated with each driver and are typically formed in the same integrated circuit.
A signalling pin is commonly reserved on the integrated circuit for each driver to communicate the results of the diagnosis processes to the microprocessor, which supervises the control of the actuator devices. At least one bit of serial information is transmitted to each signalling pin to indicate anomalies. Either a logic low or logic high value may be used depending on the logic convention. In diagnosis systems which use a single bit to indicate anomalies, it is not possible to provide the microprocessor with further information about the type of anomaly detected.
In general, more complex systems provide a description of the type of anomaly encountered using an associated code. This description is stored internally within the integrated component and transmitted to the microprocessor as a serial word, which is then reset by the microprocessor after being read. Resetting arranges the diagnosis circuit for subsequent detection of the operating state of the driver. The code adopted includes a number of available bits to represent n separate combinations, of which nxe2x88x921 combinations are reserved for the description of anomalies and one combination is reserved for coding the condition of xe2x80x9cno anomaly detected.xe2x80x9d
Turning now to FIG. 1, a prior art diagnosis system for a driver D is illustrated in which the driver is a so-called xe2x80x9clow-sidexe2x80x9d type that is supplied from a voltage supply source VAL. A microprocessor control unit (not shown) provides the driver D with a logic control signal IN. For convenience, the actuator device which is controlled by the driver D via a driving signal Vout is also not shown. The driver D is controlled in one of two possible operating phases as a function of the state of conduction of an electronic witch Q, which may be a MOSFET transistor, for example. The switch Q is driven at a control electrode by the logic control signal IN.
A first node A and a second node B of the driver D are connected to the inputs of corresponding first and second comparator circuits 10, 20. Both first and second comparator circuits 10, 20 also receive at their inputs the logic control signal IN from the microprocessor. The first comparator circuit 10 also receives an input short circuit to battery reference voltage Vshb. The second comparator circuit 20 receives an input short circuit to ground reference voltage Vshg and an open circuit to load reference voltage Vopen.
In a simple embodiment, the comparator circuits 10 and 20 respectively include one and two threshold comparator circuits to provide output logic diagnosis signals F1, F2, F3. The logic diagnosis signals F1, F2, F3 respectively indicate of the presence or absence of the anomalies short circuit to battery, short circuit to ground, and open circuit to load. The diagnosis signals F1, F2, F3 are transmitted to a memory and coding circuit MC which outputs a coded word on a state bus 30, where the coded word represents the detected operating state. The capacity of the state bus 30 is based upon the number of anomalies which the system is able to detect. In this example, since it is desired to recognise the above listed anomalies plus a condition of xe2x80x9cno detected anomalies,xe2x80x9d only two bits are provided to convey this information.
The state bus 30 is connected to the input of a serial peripheral interface SPI, which also receives similar inputs from other diagnosis systems in the same integrated circuit. The serial peripheral interface SPI can be selected by the microprocessor of the control unit and can transmit the detected information to the microprocessor in a synchronised manner via a signalling pin 32. The memory and coding circuit MC is reset by the microprocessor via the reset signal RESET_MC once transmission has taken place.
The microprocessor is programmed to perform a recognition procedure for detecting the presence of anomalies and their extinction, and to drive the actuator device as a function of the recognised operating state of the corresponding driver. The microprocessor does not know the operating phase of the individual drivers (for example ON, OFF, high impedance) because the monitoring of such phases is usually delegated to an external time programming unit (TPU). As such, it is important that the microprocessor does not receive erroneous information about the presence or absence of anomalies.
A conventional diagnosis circuit is able to detect a given anomaly only in particular operating phases of the driver. For example, anomalies such as short circuit to battery in a driver of the type described above can only be detected during an activation (ON) phase of the circuit. Anomalies such as a short circuit to ground or an open circuit to load condition can only be detected during a phase in which the circuit is not active (OFF).
Accordingly, each time the information relating to an anomaly is reset, this anomaly cannot be further detected if the operating phase of the driver is simultaneously changed, even if the anomaly is still present. In such a case the operating state of the driver is identified by a xe2x80x9cno anomaly detectedxe2x80x9d condition, and the microprocessor then erroneously proceeds to recognize extinction of the previous anomaly.
A further disadvantage of the prior art is the possibility of not detecting anomalies even during the operating phase of the driver in which they can be recognised. That is, between two consecutive readings by the microprocessor of the control unit, the memory and coding circuits of the prior art only detect and store the first anomaly encountered after resetting the information in the memory. Thus, subsequent anomalies are ignored, thereby causing an updating loss in the control unit.
An object of the present invention is to provide a system for diagnosis of a driver which overcomes the above disadvantages.
Another object of the present invention is to provide a coding of the anomalies that does not cause errors in recognition by the microprocessor; that is, to provide a coding of xe2x80x9cno anomaly detectedxe2x80x9d only if the system has ascertained this condition during each of the operating phases of the driver. The system distinguishes the condition of xe2x80x9cno detected anomaly in each operating phasexe2x80x9d from a plurality of conditions of xe2x80x9cno detected anomaly in the current operating phase.xe2x80x9d
A further object of the present invention is to provide a diagnosis system that is able to detect and code the last anomaly occurring in a series of concurrent anomalies, and that allows the control unit to perform a correct updating on the operating state of the driver under examination.
According to the invention, whenever an anomaly is detected, its presence is stored in a corresponding memory circuit, thus resetting information corresponding to other types of anomalies which may have been previously detected. Downstream of the memory circuit the system has a sequential logic network which receives input information updated to a last detected anomaly. The sequential logic network is a state machine and codes the operating state of the driver as a function of the detected anomalies.
The state machine receives a number of input logic signals equal to the number of anomalies recognisable by the system, a system reset signal indicating that the reading by the control unit has occurred, and a driver control signal indicating the current operating phase. The sequential network achieves an internal state corresponding to an operating state of the driver as a function of the received input logic signals. The sequential network makes available to a microprocessor (or to a serial interface circuit) a word of N bits on an output bus to describe the detected operating state.
In particular, if n anomalies are to be detected and there are k possible operating phases of the driver, the state machine recognises n operating states corresponding to the presence of each anomaly, k operating states corresponding to the condition of xe2x80x9cno detected anomaly in the current operating phasexe2x80x9d, and one operating state corresponding to the condition of xe2x80x9cno detected anomaly in each operating phase.xe2x80x9d As such, the value N will be defined by the equation 2Nxe2x89xa7n+k+1.
Further improvement may be achieved by the use of an auxiliary driving module located in the path of the driver control signal leading to the driver. The auxiliary driving module allows the driver to be deactivated upon detection of an anomaly even in the operating phase in which the driver is activated by the control unit (i.e., the ON phase). This allows reactivation of the driver as soon as the control unit reads its operating state, which is followed by a resetting of the system. In addition, the auxiliary driving module is set up to deactivate the driver again whenever the system detects that the anomaly remains.